SampledClocks

This model demonstrates that the sampled clock signals are different. The sampled continuous clock signal has some delay compared with the sampled discrete clock signal. The delay is the the sample period of the sampler. As the sample period goes to 0.0, the delay goes to 0.0.

The cause of the delay can be interpreted as samplers only sample the signals with some set up time.

Caution: The model shows a deterministic behavior of the samplers, while in reality, non-deterministic behaviors caused by the timer issues usually can not be avoided. We don't recommend to use sampler to sample the signals with discontinuities in models design.

The block diagram for the model was constructed using the Ptolemy II schematic editor called Vergil.