The cause of the delay can be interpreted as samplers only sample the signals with some set up time.
Caution: The model shows a deterministic behavior of the samplers, while in reality, non-deterministic behaviors caused by the timer issues usually can not be avoided. We don't recommend to use sampler to sample the signals with discontinuities in models design.
The block diagram for the model was constructed using the Ptolemy II schematic editor called Vergil.