A Coupled Hardware and Software Architecture
for Programmable Digital Signal Processors

Edward A. Lee

Ph.D. Dissertation
Technical Memorandum No. UCB/ERL M86/54
June 10, 1986
Electronics Research Laboratory
College of Engineering
University of California, Berkeley 94720




The main objective of this thesis is to propose techniques that will help harness the potential of VLSI for high performance, real-time digital signal processing. Ideally, state of the art implementation techniques will be within the reach of the algorithm developers, communications specialists, numerical analysts, and signal processing specialists. Currently, a major technological chasm separates these individuals from the hardware and software tools required to implement and test their ideas in real-time. In spite of slow steady progress with silicon compilation, chip design still requires a circuit designer to do the layout. The language of a circuit designer is usually foreign to the communications specialist with an interest in estimation, adaptive filters, or distributed control. Software implementation techniques are not much better. Although significant progress has been made with software interfaces on general purpose computers, such machines often cannot approach real-time, and interfacing such machines in real environments is often difficult even for the architecture specialist. High performance architectures, such as programmable monolithic DSP chips, usually require specialized programming in assembly language, complicated by extensive pipelining and parallelism.