EE290N - Specification and Modeling of Reactive Real-Time
Systems
Lecture 4 - September 5, 1996,
Scribe: Amit Mehrotra
Synchrony
Two events are synchronous if they have the same tag. Two signals are
synchronous if all the events in one signal are synchronous with an
event in the other signal. A system is synchronous if every signal in
the system is synchronous with every other signal in the system.
By the above definition, Synchronous Dataflow model of computation is
not synchronous. The "synchronous languages" are synchronous if we
consider bottom in the set of signals. Infact all timed systems are
synchronous if we can identify a bottom.
Discrete Event Simulators
In the "full abstraction" model, the question whether the simulator
is accurate or not is equivalent to asking whether the operational
semantics and the denotational semantics coincide or not. This is a
difficult question to answer for typical discrete event simulators.
In the context of discrete event simulators we have
- Event Queue
- Sorted list of pending events.
- Current Time
- Smallest tag in the queue.
The simulator looks for the first unprocessed event in the event queue
and activates all the processes which have that event as an
input. This might generate new events which are also included in the
event queue. These new events cannot have a tag smaller than the
current time. For a closed system, the simulator looks for "output
only" processes and they are determinate, simulation can start. The
simulation process "sees" events only up to the current time. However
the simulator is typically implemented on a sequential computer and so
the problem arises when dealing with events with identical tags. The
simulator will execute one event after the other with no particular
order but different orders could cause different results. Also some
functions could result in the output being non-functional. For instance
the function "merge" produces an output which is non-functional if
the two inputs are synchronous. VHDL is an example of a discrete event
simulator.
VHDL ensures strict causality by introducing the additional notion of
delta time steps where the current time is not advanced. Thus if an
event causes another event to happen at the same time, in simulation
this resultant event actually occurs delta time step after the main
event. For instance, for the first example in lecture 4, if P2 gets
executed before P1, P2 will be rescheduled to be executed after a
delta time step once P1 has executed. It can be shown that the result
of the simulator will be the same irrespective of the order of
execution of P1 and P2.
It will be shown later that strict causality ensures determinacy.