Within the VHDL domain there are a number of different
Targets to choose from. The default target, default-VHDL, generates sequential VHDL code in a single process within a single entity, following the execution order from the SDF scheduler. This code is suitable for efficient simulation, since it does not generate events on signals. The SimVSS-VHDL target is derived from default-VHDL and it provides facilities for simulation using the Synopsys VSS VHDL simulator. Communication actors and facilities in the SimVSS-VHDL target support code synthesis and co-simulation of heterogeneous CG systems under the CompileCGSubsystems target developed by José Luis Pino. There is also a SimMT-VHDL target for use with the Model Technology VHDL simulator. The struct-VHDL target generates VHDL code where individual actor firings are encapsulated in separate entities connected by VHDL signals. This target generates code which is intended for circuit synthesis. The Synth-VHDL target, derived from struct-VHDL, provides facilities for synthesizing circuit representations from the structural code using the Synopsys Design Analyzer toolset. Because the VHDL domain uses SDF semantics, it supports retargeting from other domains with SDF semantics (SDF, CGC, etc.) provided that the stars in the original graph are available in the VHDL domain. As this experimental domain evolves, more options for VHDL code generation from dataflow graphs will be provided. These options will include varying degrees of user control and automation depending on the target and the optimization goals of the code generation, particularly in VHDL circuit synthesis.Unlike the VHDL domain, the older and less-developed VHDLB domain is much simpler in its operation. When a universe in the VHDLB domain is run, the graph is traversed and a codefile is generated in a pop-up window and in a subdirectory which reflects the topology and hierarchy of the graph. The generated VHDL code will reference VHDL entities which are expected to be included in other files. There is a VHDL codefile in the
$PTOLEMY/src/domains/vhdlb/lib directory for each VHDL star in the main star palettes of the $PTOLEMY/src/domains/vhdlb/icons directory. Adding a new star is a matter of writing VHDL code for the entity and adding a star file in the stars subdirectory of the VHDLB domain which reflects the inputs, outputs, and parameters of that star. The existing stars should serve as examples for how new stars can be written.Table 4-1 below summarizes the various domains
