Architecture Papers

Although this is neither up-to-date nor comprehensive, below is a list of selected papers about computer architecture for embedded systems.

  1. Michael Zimmer, "Predictable Processors for Mixed-Criticality Systems and Precision-Timed I/O, PhD Thesis, EECS Department, University of California, Berkeley, Technical Report No. UCB/EECS-2015-181, August 10, 2015.
  2. Hokeun Kim, David Broman, Edward A. Lee, Michael Zimmer, Aviral Shrivastava, and Junkwang Oh, A Predictable and Command-Level Priority-Based DRAM Controller for Mixed-Criticality Systems, in Proceedings of the 21st IEEE Real-Time and Embedded Technology and Application Symposium (RTAS), Seattle, pp 317-326, WA, USA, April 13-16, 2015.
  3. Michael Zimmer, David Broman, Chris Shaver, and Edward A. Lee. FlexPRET: A Processor Platform for Mixed-Criticality Systems, In Proceedings of the 20th IEEE Real-Time and Embedded Technology and Application Symposium (RTAS), Berlin, Germany, April 15-17, 2014.
  4. David Broman, Michael Zimmer, Yooseong Kim, Hokeun Kim, Jian Cai, Aviral Shrivastava, Stephen A. Edwards, Edward A. Lee. Precision Timed Infrastructure: Design Challenges. In Proceedings of the Electronic System Level Synthesis Conference (ESLsyn), Austin, Texas, USA, May 31-June 1, 2013.
  5. Isaac Liu, Jan Reineke, David Broman, Michael Zimmer, Edward A. Lee. A PRET Microarchitecture Implementation with Repeatable Timing and Competitive Performance, In Proceedings of the 30th IEEE International Conference on Computer Design (ICCD), Pages 87-93, October, 2012.
  6. Isaac Liu. Precision Timed Machines, Ph.D. Dissertation, EECS Department, University of California, Berkeley, Technical Report No. UCB/EECS-2012-113, May 14, 2012.
  7. Jan Reineke, Isaac Liu, Hiren D. Patel, Sungjun Kim, Edward A. Lee, PRET DRAM Controller: Bank Privatization for Predictability and Temporal Isolation, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October, 2011.
  8. Dai Nguyen Bui, Edward A. Lee, Isaac Liu, Hiren D. Patel, Jan Reineke. Temporal Isolation on Multiprocessing Architectures, Design Automation Conference (DAC), June, 2011.
  9. Stephen A. Edwards, Sungjun Kim, Edward A. Lee, Isaac Liu, Hiren D. Patel, Martin Schoeberl. A Disruptive Computer Design Idea: Architectures with Repeatable Timing, Proceedings of International Conference on Computer Design (ICCD), IEEE, Lake Tahoe, CA, 4-7 October, 2009.
  10. Ben Lickly, Isaac Liu, Sungjun Kim, Hiren D. Patel, Stephen A. Edwards and Edward A. Lee, Predictable Programming on a Precision Timed Architecture, in Proceedings of International Conference on Compilers, Architecture, and Synthesis from Embedded Systems (CASES), October, 2008.
  11. Stephen A. Edwards and Edward A. Lee, The case for Precision Timed (PRET) Machines, in Proceedings of the 44th annual conference on Design Automation Conference (DAC), San Diego, California, pp. 264-265, June, 2007.
  12. S. Sriram and E. A. Lee, "Determining the Order of Processor Transactions in Statically Scheduled Multiprocessors," Journal of VLSI Signal Processing, Vol. 15, No. 3, pp. 207-220, March 1997.
  13. E. A. Lee and J. Bier, "Architectures For Statically Scheduled Dataflow," Journal on Parallel and Distributed Systems, December 1990.
  14. E. A. Lee, "Programmable DSP Architectures, Part II," IEEE Acoustics, Speech, and Signal Processing Magazine, vol. 6, no. 1, pp. 4-14, January, 1989.
  15. E. A. Lee, "Programmable DSP Architectures, Part I," IEEE Acoustics, Speech, and Signal Processing Magazine, October, 1988.
  16. E. A. Lee and D. G. Messerschmitt, "Pipeline Interleaved Programmable DSPs: Architecture," IEEE Trans. on Acoustics, Speech, and Signal Processing, vol. ASSP-35(9), September, 1987.