DESIGN AND IMPLEMENTATION OF AN ORDERED MEMORY ACCESS ARCHITECTURE

by
S. Sriram and E. A. Lee

Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing
Minneapolis, MN, Vol. I pp. 345-348, April 1993

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ABSTRACT

This paper describes a multiprocessor machine for real-time Digital Signal Processing that uses commercial programmable DSP chips. The architecture is a shared memory, single shared bus parallel processor designed to run signal processing tasks that can be statically scheduled.The design is based on the architecture proposed in [1]. A prototype has since been built. The implementation details and performance results are discussed here.

1. This work was supported by grants from SRC (grant number 92-DC-008), Motorola Inc., and ArielCorp.