Ptolemy Project Papers for 1993

  1. Shuvra S. Bhattacharyya and Edward A. Lee, "Scheduling Synchronous Dataflow Graphs for Efficient Looping," J. of VLSI Signal Processing, vol. 6, December 1993.
  2. Asawaree Kalavade and Edward A. Lee, "Hardware/Software Codesign Using Ptolemy," Proc. of IEEE Int. Workshop on Hardware/Software Codesign, Estes Park, Colorado, September, 1992. Selected by IEEE Design and Test for publication in a special issue, September 1993.
  3. S. S. Bhattacharyya, J. T. Buck, S. Ha, and E. A. Lee, "A Scheduling Framework for Minimizing Memory Requirements of Multirate DSP Systems Represented as Dataflow Graphs," in VLSI Signal Processing VI, IEEE Special Publications, New York, 1993.
  4. Joseph T. Buck, "Scheduling Dynamic Dataflow Graphs with Bounded Memory Using the Token Flow Model," Tech. Report UCB/ERL 93/69, Ph.D. Thesis, Dept. of EECS, University of California, Berkeley, CA 94720, 1993.
  5. Asawaree Kalavade and Edward A. Lee, "A Hardware/Software Codesign Methodology for DSP Applications," IEEE Design and Test, September 1993, vol. 10, no. 3, pp. 16-28.
  6. Praveen K. Murthy, "Multiprocessor Code Synthesis in Ptolemy," Tech Report UCB/ERL 93/66, Master's Report Dept. of EECS, University of California, Berkeley, CA 94720, July 1993.
  7. Gilbert C. Sih and Edward A. Lee, "Declustering: A New Multiprocessor Scheduling Technique," IEEE Trans. on Parallel and Distributed Systems, vol. 4, no. 6, pp. 625-637, June 1993.
  8. Kennard D. White, "XPole: An Interactive Graphical Signal Analysis and Filter Design Tool," Master's Report, UCB/ERL M93/70, Dept. of EECS, University of California, Berkeley, CA 94720, May 1993. See also XPole 1.4.5 manual.
  9. S. S. Bhattacharyya, J. T. Buck, S. Ha, E. A. Lee, "Generating Compact Code from Dataflow Specifications of Multirate DSP Algorithms," UCB/ERL Technical Memorandum M93/36, May 21, 1993.
  10. S. S. Bhattacharyya, J. T. Buck, S. Ha, E. A. Lee, "A Compiler Scheduling Framework for Minimizing Memory Requirements of Multirate DSP Systems Represented as Dataflow Graphs," UCB/ERL Technical Memorandum M93/31, March 25, 1993.
  11. Shuvra S. Bhattacharyya and Edward A. Lee, "Looped Schedules for Dataflow Descriptions of Multirate DSP Algorithms," UCB/ERL Technical Memorandum UCB/ERL M93/37, May 21, 1993.
  12. José L. Pino, "Software Synthesis for Single-Processor DSP Systems Using Ptolemy," Master's Report, UCB/ERL M93/35, Dept. of EECS, University of California, Berkeley, CA 94720, May 1993.
  13. John R. Barry, Edward A. Lee, and David G. Messerschmitt, "Capacity Penalty due to Ideal Zero-Forcing Decision-Feedback Equalization," Proc. of IEEE Int. Conf. on Communications, Geneva, Switzerland, May 1993, vol. 1, pp. 422-427.
  14. J. R. Barry, J. Kahn, W. J. Krause, E. A. Lee, and D. G. Messerschmitt, "Simulation of Multipath Impulse Response for Indoor Wireless Optical Channels," IEEE Journal on Selected Areas in Communications, vol. 11, no. 3, pp. 367-379, April 1993.
  15. Joseph T. Buck and Edward A. Lee, "Scheduling Dynamic Dataflow Graphs with Bounded Memory Using the Token Flow Model," Proc. of IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, Minneapolis, MN, April, 1993, vol. I, pp. 429-432.
  16. Sundararajan Sriram and Edward A. Lee, "Design and Implementation of an Ordered Memory Access Architecture," Proc. of IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, Minneapolis, MN, April, 1993, vol. I, pp. 345-348.
  17. Edward A. Lee, "Representing and Exploiting Data Parallelism Using Multidimensional Dataflow Diagrams," Proc. of IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, Minneapolis, MN, April, 1993, vol. 1, pp. 453-456.
  18. G. Borriello, K. Buchenrieder, R. Camposano, E. A. Lee, W. H. Wolf, "Hardware/Software Codesign: D&T Roundtable in cooperation with the IEEE/ACM First International Hardware/Software Codesign Workshop," IEEE Design and Test of Computers, March 1993.
  19. S. S. Bhattacharyya, J. T. Buck, S. Ha, E. A. Lee, "A Compiler Scheduling Framework for Minimizing Memory Requirements of Multirate DSP Systems Represented as Dataflow Graphs," UCB/ERL Technical Memorandum M93/31, March 25, 1993.
  20. Gilbert C. Sih and Edward A. Lee, "A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures," IEEE Trans. on Parallel and Distributed Systems, vol. 4, no. 2, February, 1993.
  21. Edward A. Lee, "Multidimensional Streams Rooted in Dataflow," Proc. IFIP WG10.3 Working Conference on Architectures and Compilation Techniques for Fine and Medium-Grain Parallelism (Orlando, FL, USA January, 1993), North-Holland, New York, 1993.
  22. Joseph T. Buck, "The Ptolemy Kernel, A Programmer's Companion for Ptolemy 0.4," Memorandum UCB/ERL M93/8, January 19, 1993.
  23. Shuvra S. Bhattacharyya, Soonhoi Ha, and Edward A. Lee, "Single Appearance Schedules for Synchronous Dataflow Programs," Memorandum UCB/ERL M93/4, January 10, 1993.